- 邏輯合成
- 邏輯綜合
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logic synthesis中文什么意思
例句與用法
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- Logic synthesis logic synthesizer
邏輯合成邏輯合成器 - ( 4 ) design and implement the alogrithm " delay balance in multiple level logic synthesis "
( 4 )設(shè)計(jì)并實(shí)現(xiàn)了“多級(jí)邏輯綜合延遲均衡”算法。 - 2 . the logic synthesis process is studied in detail and the relative constraints are discussed
2 .詳細(xì)研究了soc應(yīng)用設(shè)計(jì)流程中的邏輯綜合技術(shù)方法。 - 2002 , 149 : 119 - 128 . 9 sasao t . switching theory for logic synthesis . kluwer academic publishers , london , 1999
通過對(duì)給定的fprm真值矢量進(jìn)行收縮,獲得收縮后的真值矢量,然后把該矢量映射成邏輯表示式。 - This dissertation detailedly investigate the symbolic logic and some typical techniques for low power fsm logic synthesis and optimization
論文詳細(xì)討論了低功耗有限狀態(tài)機(jī)綜合與優(yōu)化中的符號(hào)邏輯和一些典型方法。
百科釋義
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog.
詳細(xì)百科解釋